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The authors give a broad overview of some of the possible (and actual) applications of rapid thermal processing (RTP) techniques. Pioneering work done in the.
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Thus, it is desirable to be able to subject the implanted semiconductor wafers to RTA while at the same time obtaining a high quality surface without any slip lines. Additionally, it is desirable to substantially avoid presence of EN1 trapped defects in the RTA treated wafers.


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The problems outlined above may be overcome by means of the invention set out in the claims. In an exemplary process according to the invention, a wafer to be annealed is placed within a "black-box" comprising a base, a guard ring and a lid which is then positioned within an annealing chamber. The black-box is of a material which substantially absorbs incident radiation energy and dissipates energy principally by radiation.

The RTA of the wafer annealed within the black-box results in wafers substantially free of slip lines. RTA carried out as a three-step anneal leads to reproducibly high mobilities and uniform activation. The three-step RTA includes a pre-anneal step at a temperature and for a period of time sufficient to reduce thermal shock to the wafer which otherwise may result from higher annealing temperatures, a main anneal step at a temperature and for a period sufficient to remove damage caused to the semiconductor surface by ion implantation and to activate dopant ions, and a post-anneal step at a temperature and for a period sufficient to relieve stresses resulting from the main-anneal step.

The use of the three step RTA in combination with the black-box leads to wafer substantially free of slip lines and with reproducibly high mobilities and uniform activation.


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  • A technique and apparatus for annealing wafers by RTA with avoidance of slip lines and with reproducibly high mobilities and uniform activation are described below. Si-implanted GaAs wafers are being used as exemplary semiconductor wafers for illustrating the invention. Other semiconductor materials and other dopants may be treated with logical modifications utilising the hereinbelow described teachings.

    Prior to the RTA, the implanted wafers were capped encapsulated with a film of e-beam deposited glass in a thickness within a range from 10 to nm. For annealing purposes, a PSG film within a range of from 30 to nm, typically approximately nm thick, is adequate. Also, presence of phosphorus inhibits further diffusion of, e. Under these conditions, the glass layer forms a good barrier without stressing the semiconductor surface.

    Amounts below 1 mole percent may still significantly reduce stress, however, only marginally reducing the glass softening temperature. Patent 4,, issued on March 15, to D. Ekholm et al. The phosphosilicate glass may be very effectively and inexpensively prepared for use in e-beam deposition by sol-gel technique disclosed in a co-pending U. Fleming et al. Case The use of borosilicate glass in fabrication of such devices as avalanche photodiodes is disclosed in U. Patent No. Chi et al. The use of PSG glass in preparation of various semiconductor devices including avalanche photodiodes is disclosed in the above-mentioned U.

    Patent 4,, Apparatus used for the RTA should be capable of providing thermal energy sufficient to preheat a semiconductor sample to a temperature intermediate a starting, e. A representative annealing apparatus includes a heating chamber, 3, shown in FIG. The heating chamber includes a quartz isolation tube, 4, a lower and an upper bank of high-intensity tungsten-halogen lamps, 6, and conduits, 7, for carrying a suitable cooling fluid, such as water.

    Lamps 6 emit pulsed radiant energy to heat wafer 1 placed on a tray or susceptor, 8, within the isolation tube. At low temperatures the wafer absorbs visible light, and at high temperatures it absorbs infrared radiation. Reflective surfaces, 9, are provided to reflect the heat energy toward the isolation tube and enhance the uniformity of heat energy distribution. Thermal processing occurs in isolation tube 4 between upper and lower banks of lamps 6. Tray 8 of suitable material, such as quartz, is removably positioned within isolation tube 4, and is used for supporting implanted and encapsulated wafer 1, being processed, within the tube.

    To monitor the annealing, the apparatus may be equipped with a pyrometer not shown and a thermocouple not shown. The thermocouple may be mounted in a suitable manner, such as on tray 8 beside the wafer, in contact with an underside of the wafer, or embedded in the wafer. In accordance with the invention, implanted and encapsulated wafer 1 prior to being placed on tray 8 is enclosed within an implement which may be entitled a "black-box". The implement comprises three components: a base or plate, 10, for supporting wafer 1, a guard ring, 11, for encompassing the wafer, and a lid or cover, 12, for sealing a cavity formed by the base and the guard ring.

    The black box components are of a "black-body" material which absorbs substantially all incident radiation energy i. The black box components should also be of a material which is stable under operating conditions and inert with respect to the gaseous environment, e. In the illustrative example, the black box components are made of a material selected from graphite or silicon.

    RAPID THERMAL PROCESSING

    Whenever it is desired to reduce the possibility of contamination of the material of the wafer by the material s of the black box components, especially at higher RTA temperatures, at least the internally facing surfaces of these components may be covered by an encapsulating glass film. The coating may be applied in a suitable thickness, such as nm thick.

    The coating may be preferably of the same glass material as is used for capping the wafer. The inside diameter dimension of guard ring 11 is somewhat larger than the dimension of wafer 1 to be annealed so as to allow for a small clearance between the implanted wafer and the guard ring. The clearance is provided to allow for the expansion of the wafer within the cavity while allowing efficient, evenly distributed transfer of heat between the guard ring of the black box and the wafer.

    For similar reasons, the height of the guard ring is somewhat greater than the thickness of the implanted wafer so that lid 12 is also spaced from implanted wafer 1. A similar clearance is provided between the inner walls of the guard ring and the wafer.

    Rapid Thermal Processing of Semiconductors | SpringerLink

    The outside dimension of the guard ring, and thus, of the base and the lid, may be selected so as to fit within the boundaries of retainers 13 positionable on the tray within selected spacing apertures 14 FIG. Thus, for an implanted wafer approximately 5 cm. For an implanted wafer approximately 7.


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    • Different respective outside dimensions may be selected as well so as to fit a fastening arrangement of the tray being used. Prior to annealing, base 10, is placed on tray 8, guard ring 11 is placed on base 10, the implanted and encapsulated wafer 1 with the implanted side facing up is placed on base 10 within a cavity formed by guard ring 11, and then lid 12 is placed over guard ring 11 to enclose wafer 1 within the so-formed black-box.

      Alternatively, wafer 1 may be placed on base 10 prior to placing the guard ring on the base or the black box with wafer 1 may be assembled prior to placing the black box on the tray. In the particular example, the annealing cycle was a three-step anneal cycle consisting of a pre-anneal step, main annealing pulsed step and a post-anneal step, followed by a cool-down as is shown in FIG.

      This reduces the effects of the thermal shock to which the wafer would be exposed upon being subjected directly to the higher annealing temperature. A period of time of up to 50 seconds could be useful, with a period falling within a range of from 5 to 20 seconds being most suitable. All wafers annealed in this way, when examined with an optical microscope, were entirely free from thermal damage. The effectiveness of the use of the black box with a guard ring and lid of graphite or silicon in eliminating slip lines is shown in FIGs. In this experiment, four implanted and encapsulated wafers shown in FIGs.

      Wet Processing Systems for Semiconductor

      Wafers shown in FIGs. Wafer shown in FIG. The results indicate that under these conditions, the wafer was totally free of slip lines. The mere use of slow cooling rate without the graphite guard ring and lid was unsuccessful in eliminating slip lines. Results obtained with a guard ring and lid of silicon were also highly satisfactory, comparable to those obtained with the guard ring and lid of graphite. For comparison purposes wafer C was annealed upon a silicon base, but without any guard ring or lid. The slip line density in this wafer was so high as to essentially render it useless for device fabrication.

      Results obtained with a guard ring of alumina and a silicon or graphite lid were also unsatisfactory, comparable to those obtained with the guard ring of fused silica. These examples show that the use of a black-box implement including a guard ring and a lid of a black body material, such as either graphite or silicon, effectively eliminates the slip damage. A guard ring made of fused silica or alumina were found to be ineffective in preventing the slip lines.

      Similarly, unfavorable results were obtained when using guard ring and lid made of fused silica or alumina. The advantage of the three step anneal over a two step anneal including a pre-anneal and a main annealing step was explored in the following way. A number of 5 cm. The other piece of the same wafer was annealed using the three step cycle depicted in FIG. Both anneal sets were carried out with the black box with base of silicon and with guard ring and lid of graphite. When examined for slip lines, both pieces were found to be slip-free.

      This shows that the black box is effective in avoiding slip lines with either two-step or three-step RTA. However, the mobility and activity characteristics, obtainable from the two-step anneal were not as effective as those obtainable from the three-step anneal. However, average mobilities obtainable with two-step anneal were much lower than with the three-step anneal. Carrier concentration versus depth profiles were obtained from C-V measurements on a mercury probe which was calibrated against a bulk n-GaAs standard using Ti-Au Schottky-barrier diodes. A typical depth profile obtained from three-step annealing of 7.

      The LSS profile is given by the solid line. The solid curve represents the theoretical or LSS curve and is obtained by using the projected range and projected standard deviation derived from the Lindhard, Scharft and Schlott theory. Gibbon, William S. Johnson and Steven W. This difference may be explained as follows.